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Summary

An evaluation of IV measurement techniques and how this compares to the following five commercially available fault finding methods: In-Circuit Testing, Automatic Optical Inspection, X-ray Inspection, Functional Testing and Flying Probe. Results show a test strategy using a combination of these techniques provides the most cost effective and efficient means of screening faults. A demonstration board has been developed by the author as the control subject of analysis allowing verification of the FaultFinder PCI Controller against the following analytical methods: Mathematics, Simulation, Practical Tests. Each of the analytical techniques investigated produced conclusive results on functionality of the demonstration board, and each method was able to distinguish a golden board from a defective board by analysing the bode plot characteristics.

The IV Measurement techniques performed using a FaultFinder PCI Controller compares lissajous figures obtained through component measurements. Results show that parallel impedance can prevent a faulty passive component from being detected; however there is evidence to suggest there is scope for detecting active component failures. The report concludes that the FaultFinder is mostly suited for applications where no schematics or drawings are present and is used for diagnostics, not general testing. Fault diagnostic methods of lissajous figures are proposed to determine the cause of failure using Operational Region Models and X-Y Zoning methods.

Acknowledgements

Dr Janice Kiely         Project leader

Mr Ashley Longden        Lecturer

Choosing the right testing philosophy for electronic products within a company will minimise the costs of assembly. The cost to produce a printed circuit assembly comes primarily from components, manufacturing and test. Test can comprise as much as 30% of the cost of building a product. If a product is manufactured with defects, a large penalty is paid in testing and repair. Therefore test is no longer viewed as an indirect cost, but rather as an integral part of the manufacturing process, [NEAL BOB 2000] and the development of a test strategy for an electronics product is just as important as the development of the equipment itself. It is found that it costs ten times more to fix a fault at successive stages in the production process, and therefore it is more cost effective to identify faults at the earliest stage of production possible; this can be achieved by incorporating additional stages of test into the production process. [POOLE IAN 2006] Fault diagnosis is to obtain the exact information about the faulty circuit based on the analysis of the limited measured circuit responses. Fault diagnosis of analogue circuits has been one of the most challenging topics for researchers and test engineers since the 1970’s. There have been significant advances in digital fault finding; however it is still considered a ‘black art’ when dealing with the fault diagnosis of analogue circuits particularly when given the circuit topology and nominal circuit parameter values. [LIU D & STARZYK J. A 2002] Test and fault diagnosis techniques available to manufactures include; In-Circuit Testing, Automatic Optical Inspection, X-ray Inspection, Functional Testing and Flying Probe.

Currently Smiths Aerospace uses the above test techniques as part of their test strategy and wishes to investigate the possibilities of incorporating I-V measurement techniques as a manufacturing test tool and how this compares to the test methods already in service. Smiths Aerospace has purchased a FaultFinder PCI Controller developed by Diagnosys, which can take I-V measurements as detailed in Chapter 7. However due to the limited resources available within the company the FaultFinder PCI Controller has not been used. Therefore the investigation and tests performed in the dissertation in its entirety are independently undertaken by the author Peter Mayhew. A demonstration board has been developed by the author as the control subject of analysis using the following methods: Mathematics, Simulation, Practical Tests and I-V measurement techniques. The evaluation will verify the FaultFinder PCI Controller against other proven methods, and determine whether the FaultFinder PCI Controller is a suitable manufacturing tool.

The objectives of this project are:

• Investigate and evaluate In-Circuit Testing, Automatic Optical Inspection, X-ray Inspection, Functional Testing and Manual Testing
• Design and develop a circuit [Demonstration Board] which can be used for comparing measurement techniques
• Conduct a circuit analysis of the demonstration board using mathematical analysis
• Conduct a circuit analysis of the demonstration board using simulation package Multisim
• Conduct practical circuit analysis of the demonstration board
• Determine how the FaultFinder PCI Controller works
• Perform I-V measurements of the demonstration board using the FaultFinder PCI Controller
• Evaluate whether the FaultFinder PCI Controller is a suitable manufacturing tool
• To successfully manage the project within timescale given

  Methods of Fault Finding and Circuit Analysis

  Overview

In any project whether commercial or military; testing is arguably one of the most important operations during build, since this is the only way to determine if the product will be a success or failure when it reaches the customer. The project investigates a variety of commonly utilised technologies currently available in the commercial market to analyse electronic circuits, detailing and comparing their advantages and disadvantages. The testing techniques investigated are:

• Functional Testing – (ATE)
• In Circuit Testing – (ICT)
• Flying Probe
• Automatic Optical Inspection (AOI)
• Automatic X Ray Inspection (AXI)
• IV Measuring Technique – FaultFinder PCI Controller

There are more testing methods available, for example JTAG Boundary Scan. However this is outside the scope of this project, but the reader might want to consider this for verifying the solder integrity of digital components populated on circuit boards for example Ball Grid Arrays (BGA).

Functional test is usually performed at final stages of production when the product typically has limited access to only the external connectors. This is because it is risky to power-up an assembly that is fresh from construction, as the damage potential can be very high. Functional test is typically not used for diagnosing faults, but to simulate the functionality of the product by applying an input signal, and monitoring the outputs, to verify they meet the specification and ensure with a high degree of certainty the system will function correctly when dispatched. Therefore some sort of screening for electrical shorts and opens is often introduced prior to power-up. [NEAL BOB 2000].

Figure 1 Function Test Station Example [VIRGINA PANEL CORPORATION 2007]

The interface between the functional test station and board under test is typically a bed of nails and connectors, similar to the construction of the In-Circuit Tester, which allows fast connections to the board under test. Typically only connections to the inputs and outputs of the board are required, unlike an ICT. A computer running a test program controls oscilloscopes, function generators, etc, using the General Purpose Interface Bus (GPIB) protocol to control the testing equipment automatically, then recording all measurements into a text file. The test software developers write scripts which can run test scenarios multiple times, which would otherwise require a team of testers to supervise over long periods of time. This can include measuring the response times and loading the circuit. Some of the test routines can be generated automatically, however in the case of analogue designs they often need to be programmed manually which can be time consuming. A large functional test station as shown in Figure 1 can cost several hundred thousand pounds, plus the additional expense of purchasing test fixtures and programming costs. The lead lengths within the fixture can often contribute to significant capacitance, degrading the performance at which the product can be tested. [POOLE IAN 2006]

Function Test is able to perform the following tests: Functionality Testing, Load Testing, Programming IC’s

• Very fast testing, especially for digital testing.
• Much of the testing programme can be generated automatically by entering the circuit data into the tester.
• Digital boards can be programmed.
• Test Station simulations have been known to highlight race-conditions which have not been found during design and development.
• PCB’s can be quickly diagnosed with functional faults.

• High risk of damaging product if faults are present. For example solder splashes.
• ATE’s are not fast in determining the cause due to limited pin access.
• In most instances the ATE will not be able to locate a fault, unless a guided probe [manually attached via an operator] can be connected to intermediate points on the board under test.
• Programming a guided probe, and analogue testing is very time consuming. Often measured analogue values are used.
• Reduced testing performance in analogue testing due to the GPIB port waiting for test instrumentation settling down.
• In many instances the tester will be able to deduce the problem from its knowledge of the circuit.
• High cost in developing ATE’s, Plus additional fixture costs, and programming costs.

The In-Circuit Tester (ICT) is a test station comprising of computer controlled hardware which manages a matrix of drivers and sensors connected to the CUT. The board is held in place accurately by the fixture and pulled onto spring loaded pins that make contact with connections on the board as shown in Figure 2. The board may either be pulled down under the action of a vacuum or it may be achieved mechanically. [POOLE IAN 2006] After an in-circuit test is complete, the ICT can then alert the operator with a pass slip, or details of what has failed specification, and suggested comments for repair. The ICT does not test the board’s functionality, but individually tests components on board, providing there is pin access [GENRAD 2006]

Figure 2 ICT analog test hardware connections [GENRAD 2006]

There are two testing methods available for ICT TestStation; In-Circuit and Functional. Both methods can produce tests that identify a high percentage of all possible defects. In-Circuit tests are typically performed at early states of assembly to identify correct component build, and identify component faults. In Circuit Testers allows testing of each component or cluster of components (Analogue or Digital) on a board individually. Issues that arise with ICT are impedance of components in parallel with what you are measuring causing unexpected results. Since it’s impractical to remove the components for individual test, this problem is overcome by using guarding nails. Guarding nails are used when the nodes around the component under test need to be earthed in order to remove any leakage paths, providing a more accurate measurement. Effectively the component is being tested as if it was not in-circuit. [POOLE IAN 2006] If active components such as operational amplifiers are present, these are tested after the passive components with power applied. There is consideration into the order of testing by the software, so if any faults are found during the un-powered stage, no further tests are performed, to prevent any possible further damage to the circuit. Integrated circuits are tested individually for correct functional operation using test patterns drawn from a library. Techniques such as backdriving (reversing the testing polarity), disabling an inhibiting are used to make the IC appear as if it was functioning in isolation to other components.

However it is only necessary to apply an input test pattern to the IC to verify it produces the correct output response pattern. [GENRAD 2006] Manufactures generally quote a 98% fault coverage, however this ideal figure is often not achieved due i.e to larger components limiting access available to a test pad. This is due to the board under test not being designed for testability and not necessary a fault of the ICT. Due to increasing component population and decreasing pitch between components the accessibility will become more of an issue. In addition the advent of ‘stacked IC’s’ will mean current ICT techniques will need to be re-engineered. The running costs of ICT are generally less than other systems that required specialised diagnostic technicians, which makes ICT attractive for the shop floor. [POOLE IAN 2006]

Figure 3 Effectiveness of ICT [Agilent Website 2006]

ICT is able to perform the following tests, with statistics of the ICT effectiveness of finding these faults in Figure 3 : Missing components, Transposed components, Incorrect components, Short Circuits, Open Circuits, Faulty components, Programming IC’s, Test IC -Powered up, Test Bus, Testing under load.

• The ICT program can be generated automatically from Computer Aided Design (CAD) drawings. The code can then be manually adjusted where required
• High throughput, with quick diagnosis to majority of faults
• Cost effective method for screening manufacturing and component defects
• Measuring the resistances between all possible node pairs.
• Shorts and opens testing within components or on board etches
• Missing, wrong, damaged, or improperly inserted components
• Out-of-tolerance and faulty components testing
• Incorrectly programmed components and faulty memory devices testing

• With decreasing component sizes reducing access to nodes, there are more difficulties in ICT, i.e. lack of pin access
• A CUT passing ICT will still require functional testing due to limited node access
• Poor nail contact can be a issue, leading to false failures

The Flying Probe is a low cost method of testing, which is achieved via mobile probes which are moved over the board, to directly access component pins or test pads. It has a fast setup time being ‘fixtureless’ making this ideal for prototyping, due to its flexibility. The flying probe has a lower yield compared to ICT due to delays in moving the flying probe between testing points.  When available on a functional tester, the user can have the best of all worlds.  When functional test detects a failure on a circuit board output, the flying probe can be invoked to provide diagnostic capabilities.  With boundary scan also available, the tester can be provided with additional circuit state information, thus assisting fault isolation and diagnosis [UNGAR, LOUIS Y 2006]

Figure 4 Flying probe [BENCH ELECTRONICS 2007]

The major improvements are in the mechanical accuracy and electrical testing instrumentation that dramatically refine the repeatability, speed, and diagnostic capability of this test method. These enhancements allow the manufacturer to use a “golden board” as a basis for comparison to verify the attributes of items on a Bill Of Materials (BOM). [STONG JEFF 2006] In addition to analogue testing, the flying probe is also capable of powering up, boundary scan, and limited digital testing. Also incorporated is Automatic Optical Inspection, which means this technology overlaps with dedicated AOI machines. The flying probe software imports CAD data directly for the automatic generation of the test program. The arm movement sequence and coordinates are also determined through CAD data. As shown in Figure 5 the ideal probe angle is 6º which allows continued accuracy for the probe making positive contact with the target, prevention to slipping, and ensuring the probe can make contact with device pins which is in close proximity with another device. To optimise Z-plane motion as well as X-Y movement, flying probe software calculates the highest component level along the path of motion and raises the probe just above this level rather than to a generic PCB area fly height. [UNGAR, LOUIS Y 2006] Damage can be caused from the probing which has lead to techniques such as ‘soft landing’ technology as a preventative measure. Company’s using the flying probe should be aware of this potential systemic damage, and validity of the tests. Flying probe technology during the 1990’s with had typical test times of 10minutes for both sides of a PCB, which has since improved to 30-60secs allowing more widespread usage in industry. With increasing component population, this is still a concern.

Figure 5 Probe Angle [ACCULOGIC.COM 2007]

The Flying Probe is able to perform the following tests: Missing components, Transposed components, Incorrect components, Short Circuits, Open Circuits, Test IC -Powered up

• Quick program development. Setup between hours and days. Not weeks.
• There is no fixture to purchase, eliminating costly tooling procurement
• Detection incorrect parts, reversed parts, missing parts, solder opens
• Increased prototype throughput
• Analogue testing
• Faster than manual testing – 0.8 Seconds per test.
• High repeatability due to reference airlines

• Much slower than In Circuit testing, due to moving the probe around the board.
• Possible systemic damage caused by the probing
• Probing pressures can mask open circuits

Automatic Optical Inspection (AOI) uses cameras and imaging algorithms to verify correct placement and orientation of components and is also used to inspect the quality of solder joints, the presents of solder splashes and raised pins. The equipment required for AOI i.e. video cameras, visible light sources, and frame grabbers are generally off the shelve items, which makes this a favourable method of inspection compared with AXI in paragraph 4.5, which requires specialised equipment. AOI can be placed into the production line just after the solder process. In this way they can be used to catch problems early in the production process. This has a number of advantages. With faults costing more to fix the further along the production process they are found, this is obviously the optimum place to find faults. [RADIO ELECTRONICS 2006]

AOI requires time initially to learn a board, by capturing images, however the software needs to distinguish the difference between a variation in appearance from minor aesthetic deviations and true inspection failure’s. This is typically achieved by running several boards which have been manually inspected through AOI to learn the variations in production process. After this period the AOI should be reliable to inspect boards independently. AOI has two types of image inspection technology, gray scale correlation and vectoral imaging. Both of which take images of the circuit board, then compare this to a database for comparison. When using gray scale correlation, most systems store an image that is considered to be an acceptable representation of the component to be inspected. This image is later compared to other images during production and a comparison of the levels of grey of each pixel and the number of pixels that match the stored image defines whether it is worthy of being considered a good enough match to be recognised.

This is shown in Figure 7 Vectoral imaging is a pattern location search technology based on geometric feature extraction rather than absolute grey scale pixel values. Patterns are not dependent on the pixel grid. A feature is a contour that represents the boundary between dissimilar regions in an image. Features can be line segments, arcs, angles and open or closed geometric shapes, which is shown in Figure 6. [NORRIS MARK J.]

Figure 6 Vectoral Imaging [RADIO ELECTRONICS 2006]

Figure 7 Gray scale correlation. A pixelised image of a chip capacitor [RADIO ELECTRONICS 2006]

AOI is able to perform the following tests: Missing components, Transposed components, Incorrect components, Insufficient solder, Excess solder, Misaligned components, Solderballs, Marginal Joints, Physical damage to a component.

• Quick inspection of boards, highlighting common manufacturing faults
• None destructive
• Automated inspection unmanned interaction
• Preventative measure before power-up to eliminate further damage
• Equipment parts are off the shelf
• Can detect aesthetical failures ie. scratches, stains and nodules

• Continual adjustment to software sometimes required if some faults are not being recognised.
• Cannot verify components work

Automated X-Ray Inspection (AXI) is a radiograph of a printed circuit board. This shows the photographic density between different materials of the PCB, as shown in Figure 8.

Figure 8 Tranmisive X-ray image [PHOENIXXRAY 2007]

Due to increasing circuit density, companies tend to use BGA packages. Since the connections are underneath the IC the only means of inspection is AXI. X-ray laminography, is the currently the fastest growing screening technique and is the only method than can quantitatively as well as qualitatively assess solder joint integrity. What gives this inspection technique the advantage of AOI is the ability to view beneath ball-grid array packages and to view boards which are populated on both sides and multi-chip modules. [NEAL BOB 2000] Fully automatic inspection is possible of BGA, Column Grid Array (CGA), Quad Flat Package (QFP), Through-hole technology (THT) and other solder joints using specialised software packages, which imports the CAD data to teach the inspection routine. Use of AXI for printed circuit board inspection is rapidly growing, especially on high-density, complex boards. X-ray images of solder joints can be analysed automatically to detect structural defects, such as insufficient solder, voiding, shorts, opens, and other defects – that typically make up 80% to 90% of the total defects on an assembled circuit board. [LEINBACH AND ORESJO] An x-ray tube fires X-rays, which is a form of electromagnetic radiation with a wavelength 1nm to 6um, which is shown in Figure 10.

Figure 9 X Ray Inspection [PHOENIXXRAY 2007]

Figure 10 OVHM Technology [PHOENIXXRAY 2007]

It is especially useful when inspecting welds that oblique views at highest magnifications. Generally, welds are inspected by tilting the sample as shown in Figure 9. The drawback of this approach is that moving the sample while taking a radiograph decreases image sharpness causing the image to be blurred. Furthermore, the further away the sample is located from the source of radiation, the smaller the geometric magnification that can be achieved. Phoenix x-ray’s Oblique Views At Highest Magnification (OVHM) technology as shown in Figure 10 however ensures highest geometric magnifications and oblique views of up to 70 degrees by making full use of the incident X-rays by pivoting the detector instead of the sample. The transmissive property of the X-Rays is dependent on the atomic weight of the material. The higher the atomic number of a material, the more X-rays it will absorb. For example gold, with its atomic number of 79, absorbs much more X-rays than materials with lower atomic numbers, such as aluminium (Z=13), this provides the radiograph. [PHOENIXXRAY 2007]

AXI is able to perform the following tests with statistics of effectiveness shown in Figure 11: Missing components, Short Circuits, Open Circuits, Ball Grid Arrays, Insufficient solder, Excess solder, Misaligned components, Solderballs, Marginal Joints, Physical damage to a component.

Figure 11 Effectiveness of AXI [Agilent Website 2006]

• Ability to view beneath BGA packages
• X-ray images of solder joints can be analysed automatically to detect structural defects

• Training required on safety dealing with X-Ray
• Expensive
• Cannot verify components work

Managers will each have their own priorities and objectives, which include improved throughput, reduced waste, reduced rework and reduced dead boards. Without a clear focus of how this can be managed it can lead a corporate to become inefficient, thus reducing their profits. [NEAL BOB 2007]. Deciding which type of machine to utilise for test and faultfinding is crucial since this will have an affect on man-hours and therefore the production costs. Without comprehensive testing and adequate quality control, faults will be left undetected until a later stage in production, resulting in increased repair costs. Should a defective product reach the customer there is the additional risk of damaging the company’s reputation. However an over-comprehensive test strategy will reduce throughput due to particular tests being performed at board level, modular build, and final build. These repeated tests are illustrated in Figure 12. This shows for example that missing components can be identified with AXI, ICT, AOI and flying probe, and therefore it might be possible to remove one of these repeated tests. [POOLE IAN 2006]

Figure 12 Capabilities of FaultFinding equipment [Agilent Website 2006]

* IV measurement techniques discussed in Chapter 7

It is necessary to adopt a test strategy where the correct type of test is performed at the right stage of production. Inspection methods such as AOI, AXI and ICT do not guarantee the board will perform correctly, however they can filter out detective boards at an early stage of assembly and prevent further boards from being affected.

These methods are therefore mostly suited to be used at the start of production. AOI and AXI are very effective and efficient since they provide both visual and internal component inspection. Although they have limitations in their ability’s as detailed in paragraph 4.5 and 4.6, if used in conjunction with ICT they compliment each others abilities as shown in Figure 13. Functional test is focused on verifying the products performance, and is mostly suited for the final stages of production. [NEAL BOB 2007]

Figure 13 Combined effectiveness of AXI and ICT statistics [Agilent Website 2006]

Often overlooked is the data collected from the production cycle. Failure patterns can often be used to address issues within production or design to improve quality of the product. This preventative approach allows the company to concentrate on other important issues and not repeatedly fix reoccurring faults. Faultfinding will need to adapt over time with advances in manufacturing technology, since current IC’s are generally placed on a circuit board side by side, however the next generation of IC’s scheduled for production in 2008 will be constructed vertically, connected to each other by tungsten filled pipes, which are known as “through-silicon-vias”, thus eliminating the need of wires. This will make faultfinding significantly more challenging due to very limited access, and could present issues for AXI being able to distinguish faults in a the multilayered construction. Therefore it is probable that alternative methods of faultfinding will be required in the future. [BBC NEWS 2007]

In order to evaluate I-V measurement techniques using the FaultFinder PCI Controller, a circuit has been developed allowing the comparison between a golden board and a defective board using removable fault conditions. This circuit shall be referred as the Demonstration Board, which is shown in Figure 14. Ideally all common types of fault conditions should be investigated to enable a comprehensive understanding of testing techniques; however this report shall be limited to three fault conditions due to the timescale allocated. The demonstration board shall be analysed mathematically, simulation, practically and using the FaultFinder PCI Controller; evaluating the results under both working and defect conditions. The fault conditions to be investigated are:

• Fault Condition 1 : C1 36nF capacitor is replaced with a 12nF capacitor
• Fault Condition 2 : R3 10KOhm resistor is replaced with 6.8KOhm resistor
• Fault Condition 3 : Both Fault Condition 1 and Fault Condition 2

Figure 14 Demonstration Board Circuit

The demonstration board is a system comprised of linear components which can be expressed as a system of linear equations. Components such as capacitors are frequency dependent, causing the electronic circuit to change in operation with a change in frequency. One way of expressing the changes in behaviour is to construct ratios of circuit parameters and express these ratios as a function of frequency. These ratios are called transfer functions. The linear equations of the demonstration board can be represented as a form of transfer functions using the Cramer’s rule. [ZORNESKY and H. MAYBARR 2000]

The demonstration board comprises of three linear equations.

Amplifier U1     = X1

Amplifier U2     = X2

Amplifier U3     = X3

With an Input Signal    = X0

The three linear equation are as follows:

Amplifier U1 :

Amplifier U2 :

Amplifier U3:

Rearranging for X0 gives us

Amplifier U1 :

Equation 1 Simultaneous Equation U1

Amplifier U2 :

Equation 2 Simultaneous Equation U2

Amplifier U3:

Equation 3 Simultaneous Equation U3

Rearranging Equation 1, Equation 2 and Equation 3:

Solving using Cramer’s rule (x₂ is the output from circuit diagram)

The determinates are calculated using the bottom row on both the numerator and denominator matrix.

Therefore demonstration board can be expressed as the following second order transfer function:

Equation 4 Demonstration Board Transfer Function

The transfer function obtained in Equation 4 can be represented in the form of a second order transfer function shown in Equation 5.

Equation 5 Second Order Transfer Function

This is achieved by multiplying the numerator and dominator of Equation 4 by

.

This produces the following equation:

Simplifying this equation, and renaming

Converting from the frequency domain to the time domain

Suitable component values shown in Figure 15 are chosen from typical op-amp configurations.

Figure 15 Demonstration Board component values

Using the values in Figure 15 means:

With the overall expression being:

Therefore the transfer function is simplified Equation 6.

Equation 6 Demonstration Board Transfer Function

Equation 6.can also be transferred into the time domain in Equation 7, however the report shall be analysing the demonstration in the frequency domain.

Equation 7 Demonstration board equation in time domain

Figure 16 shows the magnitude is constant between 0Hz and 10Hz, which is due to the high impedance of the capacitors limiting the negative feedback. Because of capacitance within the op-amp, the gain decreases and the phase shift between input and output voltages increase as frequency increases. [GAYAKWAD, RAMAKANT A. 2000]. The roll off has a 25db/decade, this is un-usually low, since a second order circuit is typically 40db/decade for a second order circuit. This is a resultant of the negative feedback designed into the circuit, but could be changed to a 40db/decade roll off with an alternative choice of components. At 100Khz the gain rises due to the phase shift with op amps U1 and U2. The gain then stabilises at 25db for higher frequencies.

Figure 16 Mathematical analysis Bode Plot of demonstration board

The demonstration board has been designed with some instability to emphasise how a fault condition can affect the circuit’s behaviour. The instability with the demonstration board does not affect the circuit under normal working conditions in the labs in Figure 17

Figure 17 Simulation Outputs signals – Stable

Scope setting in Figure 17

ChA =50mV

ChB = 2V/div

ChC = 500mV/div

ChD = 1V/div

100Hz 20mVpp input sine wave

10ms/div

The waveforms in Figure 17 represent the following:

CH A = Input signal (Function Generator)

CH B = Op-amp U1 pin 6 [Output]

CH C = Op-amp U2 pin 6 [Output]

CH D = Op-amp U3 pin 6 [Output]

Using Matlab software the poles and zeros gain was found to be

With a gain of k = -20

Plotting using zplane(z,p) produces Figure 18.

Figure 18 Zero and Poles plotted – Circuit stability

The demonstration board has been developed in Multisim 9 with components taken from the inbuilt libraries. The bode plot, shown in Figure 19, has a similar low pass filter characteristic to the mathematical bode plot in Figure 16. The simulation shows a significant reduction in gain after 100Khz. This is a resultant of the op-amp’s internal limitations which is not taken into consideration using the laplace transforms.

A second simulated bode plot was taken of each op-amp output U1, U2 and U3. Due to the number of measurement needed, the multisim AC Analysis Tool was used with results shown in Figure 20. However the U2 phase plot in Figure 20 is unrealistic and differs from the manually obtained results in Figure 19 which are believed to be correct. The difference is due to the limited number of measurements the automatic method takes, and there is no apparent option to change this. Measurements taken from U1, U2 and U3, show the rapid phase transition at ~100Hz is a resultant of U1 and U2 shown in Figure 20. As the phases cross this will cause a change in feedback, resulting in the magnitude rising.

Figure 19 Bode Plot of simulated demonstration board

Figure 20 Bode plot of simulated circuit three outputs

With R7 open circuit, U1 and U2 was decoupled and the bode plots taken again as shown in Figure 21. There is no longer a rapid phase shift, therefore this suggests coupling of U1 and U2 was the cause of the rapid phase transition.

Figure 21 Bode plot of simulated circuit with U1 and U2 decoupled

The demonstration board practical shown are shown in Figure 22. The bode plot has a similar low pass filter characteristics as the mathematical and simulation results. Minor discrepancies are contributed from ‘real life’ conditions which are not accounted for with the mathematics and simulation. This includes parasitic capacitance (Cs), which can shunt current away from the feedback resistors (Rf) at higher frequencies, producing a response roll off with a pole at . [GRAEME, JERALD G.1996]

Figure 22 Bode Plot of demonstration board pratical test in labs

The data collected from analysing the demonstration board using the three methods detailed in Chapter 5 show similar bode plot characteristics and also verify that the circuit acts as a low pass filter. The accuracy of mathematical approach is limited since the laplace transforms do not model real-life op-amps, but treat the op-amps simply as a gain ratio. In order to obtain a more accurate mathematical representation of the demonstration board, there needs to be less mathematical assumptions. For example a transfer function of the op-amps in appose to using ratios. Despite this, matlab does provide a means for quick analysis of how the circuit should operate without building the circuit. This approach would become taxing however with an increased component population and also unrealistic to model manually if integrated circuits are implemented into the circuits design. The simulations are more closely related to the practical results since the Simulation Program with Integrated Circuit Emphasis (SPICE) models can include the transfer functions of the op-amps. However they do not include all real life conditions such as the tolerance of components. Once the circuit is built, numerous simulations, and fault conditions can be quickly introduced with minimal effort. Since the majority of manufactures or 3^rd partys provide SPICE models which include both analogue and digital component, simulation is a sensible approach to design and developing a electronic circuit. The mathematical and simulation response does remain constant at higher frequencies; however the practical circuit shows a continuous reduction in magnitude. This is due to the internal compensation within the op-amp which causes a 6db per octave roll off. The op amp also has temperature dependence, which is generally accounted for by the negative feedback. However the input offset voltage and current still has practical variations causing drift of the output voltage. [NAVE, R 2007]

The demonstration board has been retested for further mathematical, simulation and practical analysis using the fault conditions detailed in paragraph 4.1.

The transfer function for each fault condition was determined to be as follows:

Fault Condition 1 : C1 36nF capacitor is replaced with a 12nF capacitor

Simplified transfer function gives us

Equation 8 Transfer Function with C1 Fault

Fault Condition 2 : R3 10KOhm resistor is replaced with 6.8KOhm resistor

Simplified transfer function gives us

Equation 9 Transfer Function with R3 Fault

Fault Condition 3 : Both Fault Condition 1 {C1} and Fault Condition 2 {R3}

Simplified transfer function gives us

Equation 10 Transfer Function with C1 and R3 Fault

Figure 23 shows bodes plots for each fault condition, and the working condition. Each fault affects the roll off between 10Hz and 100Hz, and also changes the point of phase shift. This is due to the fault conditions changing the negative feedback of the amplifiers. This was discussed mathematically how the poles are effected in paragraph 5.4. The bode plots of each fault conditions also have noticeable difference in both magnitude and phase, therefore it is possible looking at Figure 23 to catalogue the data and use this as a fault library for future reference and diagnosis.

Figure 23 Bode plot of Mathematic Analysis with fault conditions

The demonstration board has been simulated using multisim with the fault conditions detailed in paragraph 5.1. The results are illustrated as bode plots in Figure 24 which are similar to the mathematical results in Figure 23. There is a variation in the roll off (db/decade) in the frequency response between 10Hz to ~300Hz, and the phase shift also has a slight deviation around the same region, which is due to the laplace transforms not modelling the op-amps, but treating the op-amp simply as a gain ratio. Above 1 KHz, there is negligible difference between the fault conditions. Each of the fault conditions causes a noticeable change in the phase response. The R3/C1 fault condition appears to reduce amplitude of the phase shift deviation. This is theorised to be the resultant of a reduction of negative feedback, which will increase bandwidth.

Figure 24 Bode plot of Simulated circuit with fault conditions

Given the same three fault conditions, the demonstration board was retested in the labs, and the bode plots produced in Figure 25. The frequency response shows an even distribution around the 10Hz to ~300Hz region, with similar results to both the mathematical and simulation results. The phase shift for the practical results show the R3 fault condition has a insignificant effect which is reasonable since the resistor is not a frequency dependent component.

Figure 25 Bode plot of practical circuit with fault conditions

The data collected from analysing the demonstration board with the three defective conditions each show similar bode plot characteristics, with the exception of the mathematical and simulated db magnitude reducing to 15db for the mathematical response and 20db for the simulation. This would be primarily due to the op-amp SPICE models as the accuracy of mathematical approach is limited due to the laplace transforms used since they do not model the op-amps, but treat the op-amp simply as a gain ratio. The SPICE models within the Multisim software are designed with ideal circuit characteristics. However there is typically additional capacitance within the device which is not taken into account. This is known as parasitic capacitance which is due to the physical characteristics of semiconductor devices, i.e. Bipolar Junction Transistor (BJT) and Field Effect Transistors (FET), and the internal construction of the op-amp. Also there is none ideal input and output impedances, temperature coefficients which are the resultant of a change in current flow through the internal transistors as the device changes temperature. The change in phase shift is attributed to the internally integrated capacitor(s), as well as stray capacitances. [A. GAYAKWAD, RAMAKANT 2000]

The software used to control the FaultFinder PCI Controller is Testvue

The TestVue software uses a FaultFinder PCI Controller, as shown in appendix paragraph 10.1 Figure 47. The FaultFinder utilises a method of IV testing, which measures the current and voltage flowing through a circuit. This provides the amplitude and phase relationship. The software’s is broken down into separate functions, and detailed below.

Program studio software is part of the Testvue software package and is used to develop and design the circuit layout of the board to be tested. Devices can be imported from CAD* files or created from scratch using the inbuilt FaultFinder library, see in appendix paragraph 10.1 Figure 48. This includes symbols, device package graphic outlines and test clip configurations. The Testvue, which is the order in which the components are tested is also configurable using this program, which is similar to the Genrad ICT mentioned previously, where you could test passive components before active components to limit any possible damage to the board. Alert messages can also be displayed at stages of test, which could advice on connecting test leads, or any upcoming i.e. high voltage hazards.

* Other imports such as OrCAD PCB II ™ , InterGraph, Mentor Graphics and TangoPro Net list are also available

Testvue uses a method of IV testing in which it applies a controlled alternating voltage, typically a sine wave, into the circuit node, and then displays the parametric data; voltage and current, in a variety of graphical formats. Figure 27 shows the four quadrants.

Figure 26 Testvue signature display screen area

Figure 27 Testvue signature display screen area quadrants [DIAGNOSYS 2005]

Testvue analyses the component signatures by programming / reconfiguring the AC voltage supply, which is contained on the Diagnosys PCI card to produce an AC signal which will stimulate the component under test. Both the amplitude and the frequency of the AC signal are adjustable.

The equivalent circuit of the FaultFinder PCI card is shown in Figure 28. The AC signal is variable using sixteen sensing resistors in series with the AC source. This provides the voltage / current ranges required. This can be varied from 0V to 25V and 0.1mA to 500mA. The sense resistance can be classed as a known constant, being always resistive; however the load resistance, which is the component under test, is variable as it could be resistive, inductive or capacitive. The FaultFinder PCI determines the impedance signature of Rload by measuring the voltage across Rload and Rsense. This gives us the current through Rload by ohms law V=IR. The software then displays then Rload as the horizontal (x) axis timing, and the Rsense as the vertical (y) axis timing, which is a trace representing the voltage of Rload verses the current through it. [DIAGNOSYS 2007]

Figure 28 FaultFinder Equivalent Circuit [DIAGNOSYS 2005]

Not provided in this project is an additional accessory, the scanner probe. This can provide a technician with the following benefits reducing test times

• Scanning pins up to 192 pins in a sequence via a test clip or edge connector
• Comparing two similar devices or edge connectors up to 96 pins each
• Shorts testing

Due to contact bounce of the probes, irregularities can occur when taking measurements. This is overcome using the stability check, an inbuilt function to the FaultFinder software. Enabling this option takes repetitive IV signatures and verifying that the signatures are the same. This process is repeated until the signatures are stable, or the stability check times out. By enabling this option debugging time can be reduced from ‘false fails.’

I-V measurement are parametric plots of current again voltage on an X-Y axis. These patterns are known as Lissajous Figures or Bowditch Curves.

The FaultFinder PCI controller creates digitised component signatures, represented as lissajous figures for faultfinding. Lissajous figures were discovered by Jules Antoine Lissajous, where he used them to determine the frequency of sounds and radio signals before the days of phase lock loops. A Lissajous pattern is a graph of one frequency plotted on the y axis combined with a second frequency plotted on the x axis. Y and X are both periodic functions of time t given by equations such as x = sin (w*n*t + c) and y = sin w*t. Different patterns may be generated for different values of n (period shift) and c (phase shift). The simplest patterns are formed when n is a ratio of small whole numbers such as 1/2, 2/3, or 1/3. [KRAMARCZYK MICHAEL 1999]

Measuring a resistor, will produce a linear line, where the angle is dependent on Rload. The line will rotate anticlockwise about its origin with an increase in Rload resistance.

Figure 29 Two sine waves in phase produces straight line lissajous figure

A zero ohm resistor [short circuit] will produce a vertical linear line, which has a 90 degree angle. An open circuit [infinite resistance] will produce a horizontal angle, which has an angle of 0 degrees. A resistor Rload with the same value as Rsense will provide a linear line at 45 degrees, this is illustrated in Figure 29.

This can also be proven mathematically therefore

Thus when analysing a fault condition, a shift in the signatures angle will suggest there is a resistive fault. However, the signatures are complex in that there will be parallel impedances, there is the possibility a fault could have a higher impedance than the component being measured, and therefore masking the fault from being detected.

The capacitor will produce a phase shift between current and voltage, which causing the lissajous figures to have an ellipse shape as shown in Figure 30. However the capacitors impedance is frequency dependent due to.

Figure 30 Two sine waves 90degee shift produces circle lissajous figure

Adjusting the frequency of the AC signal applied will cause the measured response to change since the capacitors impedance is frequency dependent. Figure 31, Figure 32, Figure 33 and Figure 34 show the same 0.1uF capacitance, with the lissajous figure distorted by adjusting the AC frequency applied. There is no optimum frequency or voltage with which to stimulate the test node. The default voltage & frequency is 15V & 300 Hz. The frequency is not too significant except for capacitive and inductive nodes. Too lower voltage may cause the IV measurement to not detect a fault, however too high a voltage may cause nodal instability and false results. A rule of thumb is to use the highest voltage that doesn’t cause nodal instability. [DIAGNOSYS 2007]

Figure 31 Capacitor 0.1µF (15V, 150Hz test signal).

Figure 32 Capacitor 0.1µF (15V, 300Hz test signal)

Figure 33 Capacitor 0.1µF (15V, 750Hz test signal)

Figure 34 Capacitor 0.1µF (15V, 1500Hz test signal)

The shape of a Lissajous figure from a defective circuit will be different from a normal circuit. Therefore the fault is detected by extracting the differences of these shapes. [MIURA YUKIYA 2006] Before a circuit can be tested a golden board must been learnt, which is achieved by analysing each node, and storing the signatures. Plotting the lissajous figure of an arbitrary resistor is shown in Figure 35 and an arbitrary capacitor in Figure 36. The FaultFinder PCI Controller software will be analysing the x-y co-ordinates of the measured signal, and calculating ‘on the fly’ to determine whether it’s within the upper and lower limits.

Figure 35 Resistor Lissajous Figure with 20% Tolerance

Figure 36 Capacitor Lissajous Figure with 20% Tolerance

Measurement of a 36pF capacitor the FaultFinder displays a horizontal line; representing an open circuit, which is due to the high impedance of the capacitor preventing the signature from being measured. This can be proven mathematically by

Given C = 36pF, freq=100Hz

Therefore

Thus the capacitors impedance will have insignificant effect on the lissajous figures in-circuit due to parallel impedances.

The signatures of R3 and C1 in a working state are shown in Figure 37 and Figure 38 respectively. The R3 signature in Figure 37 shows a phase shift between the current and voltage in quadrant 4, and no phase and amplitude difference in quadrant 2/3. The C1 signature in Figure 38 shows there a phase shift between the current voltage in quadrant 4, and a small phase and amplitude difference in quadrant 2/3.

Figure 37 R3 Lissajous Figure. No fault

Figure 38 C1 Lissajous Figure. No fault condition

R3 is replaced with a 6.8KOhms resistor (Fault condition 2) and retested. The lissajous figure is shown in Figure 39. There is no change in the lissajous figure; and the fault is not detected using the Faultfinder. C1 is replaced with a 12nF capacitor and retested. The lissajous figure is shown in Figure 40. There no change in the lissajous figure, and the fault is not detected using the faultfinder. Comparison of the fault free and fault lissajous figures shows insignificant differences and the FaultFinder software is unable to distinguish a fault condition, hence always producing a PASS.

Larger lissajous diagrams can be founding appendix

Figure 39 R3 Lissajous Figure. Fault condition

Figure 40 C1 Lissajous Figure. Fault Condition

Chapter 4 investigated the methodologies of five commercially available fault finding methods: Functional Testing, In-Circuit Tester, Flying Probe, Automatic Optical Inspection and Automated X Ray Inspection (laminography). The evaluation shows there is no fixed test strategy which would be suitable for all company’s to implement. The company needs to assess their own requirements given the circuit topology and technology implemented into their product. A comparative example would be a company developing a high voltage power supply which would require testing of large passive components; this would plausibly have straightforward access to test pads. However a company developing a digital mobile phone is more likely to incorporate a fabrication method using densely populated integrated circuits which has limited pin access, or no pin access in the case of Ball Grid Arrays. In the majority of cases a company should use at least AOI or AXI to ensure quality of build; however paragraph 4.7 has evidence to show that a combination of these two would be more effective for screening out defective boards. ICT will give confidence whether the product will work when powered up, however this should not be used as a definitive means of verifying the board meet specification as ICT is unlikely to have 100% coverage. In addition ICT tests the components, not the board’s functionality. The report shows evidence in paragraph 4.7 that ICT used in combination with AOI and AXI is an effective method for verification of build during assembly. Functional test verifies the product meets the specification, and should be mandatory at the final stages of build. The test strategy used should also ensure that the combinational use of methods are not over-comprehensive as this will lead to reduced throughput from tests being performed at board level, modular build, and final build. Once a test strategy is in place, it should be reviewed regularly to ensure it remains to be the most cost effective solution due to the evolvement in component packages and improvements in test / inspection equipment available.

Each of the analytical techniques investigated produced conclusive results on functionality of the demonstration board, and each method was able to distinguish a golden board from a defective board by analysing the bode plot characteristics. The mathematical model can be applied to any circuit since any circuit can be expressed as a transfer function, however the complexity of the transfer function will inevitably become impractical to manually resolve with increasing component population. Thus, the limiting factors are time in determining the transfer function, and the possibility of errors being introduced through human error. It is more advantageous to utilise the computational prowess of simulators such as multisim and minimise on human errors. The simulator is simply a range of SPICE models, each having their own transfer functions. As components are modelled or instances taken from the library, their parameters can be individually adjusted to meet the designer’s specifications. Effectively the SPICE models are building blocks, allowing efficient design of a circuit, and its overall transfer function is determined by the individual blocks and how they are interconnected.

The bode plots of the mathematical model and simulation confirm this, as the results are practically identical. This is to be expected. Both methods exclude real life characteristics such as tolerance, parasitic capacitance, temperature coefficients, true input and output impedance and other variations. The demonstration board was built and tested, and the bode plots created from the results confirmed with the mathematics and simulations, taking into account the real-life conditions discussed. This leads us to IV measurement techniques, and whether this is a viable alternative to more traditional methods of AXI, AOI and ICT. This report has found some weaknesses with the IV measurement technique. Whilst the FaultFinder will detect passive component faults, the component had to be significantly out of tolerance to be detected. This would have caused potential failures to be undetected within production. However faults such as transposed IC’s are easily detected which is detailed in Further Work in paragraph 8.1.1. Idealistically it would be preferable to have a single testing method in which can encompass all possible fault conditions, however this report shows this is not been possible in real life conditions. Each technique has its own benefits and weaknesses. ICT has many sophisticated techniques to detect and isolate the cause of faults. This includes the use of guard nails which removes leakage current from devices under test, effectively isolating the component from the rest of the circuit.

If the FaultFinder could incorporate the IV measurement techniques into an automated process, where either a bed of nails or flying probe approach is used, then IV measurement could become a practical means of test, however it’s unlikely this technology can be used to adequately screen out defective components within production as this stands. It is the opinion of this report that the FaultFinder is mostly suited for applications where no schematics or drawings are present and this technology is used as a alternative methods for diagnostics, not general testing. Unless the scanner option is purchased as part of the FaultFinder kit, the FaultFinder could become a bottleneck with production throughput since it is primarily dependent on the operator’s dexterity in moving the probes quickly between test pads, which could be a problem on highly populated boards. However given the low set up costs and the simplicity of comparing component signatures, the FaultFinder should be considered for certain company contracts. The results from this report do not show sufficient evidence to support the Dianogsys claims that: ‘The FaultFinder can trouble-shoot any un-powered circuit board no matter what component configuration is involved. Linear or digital integrated circuits, wound components or discrete devices all are subject to the FaultFinder’s scrutiny’, however there is evidence detailed in further work to suggest possible usage of active component fault detection in paragraph 8.1.1.

Although a fault conditions can been detected, there is no automatic assistance in diagnosing the cause of the failure. This is currently dependent on the experience of the operator, as the Testvue software provided does not extract any information from the lissajous figures. There is however three options which this report can propose:

• The creation of a fault library. By storing the defective component signatures, this can be used as reference to diagnose future faults. However there is currently no automatic way of doing this.
• The IV measuring techniques could be further investigated by utilising the Operational Region models and X-Y zoning methods on the lissajous figure to determine which component within the circuit is the cause of the fault, further details can be found in paragraph 8.1.2
• Moving the common reference points for the FaultFinder might provide improved testability in finding faults with passive components.

The long term solution for a company would be correct the process failures within production which would lead to less rework and waste and increased throughput and yields, leading to higher profits.

The results from the FaultFinder do not show sufficient evidence to suggest this tool is capable of detecting faults on the demonstration board; however the faults investigated was limited to passive components. The demonstration board was retested with a transposed Integrated Circuits (IC) monitoring pin 6 and 7 of the 741 op amp. In both conditions the FaultFinder did reliably detect the faults. The ‘no fault condition’ shown in Figure 41 and Figure 42, and the ‘fault conditions’ shown in Figure 43 and Figure 44.

Figure 41 IC3 Pin 6 No fault

Figure 42 IC3 Pin 7 No fault

Figure 43 IC3 Pin 6 IC transposed fault

Figure 44 IC3 Pin 7 IC transposed fault

In recent years a test method for analogue circuits called the X-Y zoning method has been proposed. This method utilises the relationship of the voltage characteristics between the input and output of a circuit (or between the input and observation nodes) with lissajous figures drawn to plot the relationship on the X-Y plane. The shape of the lissajous figure of the faulty circuit will be different from that of a normal circuit if a fault is detectable. Therefore, the fault is detected by extracting the differences of these shapes. This is similar to the methods used in this report to diagnose the faults on the demonstration board. Each MOS transistor in a normal circuit operates in any of the following Operation Regions (OR): the Cutoff region (C), the Linear region (L), or the Saturation region (S). The region will change for the OR of several transistors inside a circuit depending on external input values or in response to the presence of a fault. Therefore, the behaviour of circuits constructed using MOS transistors can be modelled by observing the OR of the MOS transistors and utilising those characteristics. This type of modelling method is called an operation-region model (OR model) and as shown in Figure 46. Although OR models can represent circuit behaviour by observing the OR of a transistor as the internal state of the circuit it cannot directly find the effects on the items being from outside the circuit. Although X-Y Zoning method can detect faults by observing the input and output characteristics of a circuit it is difficult to directly find changes in the internal state due to faults. Therefore it is considered a combinational use of both the OR model and X-Y Zoning method to balance each of the drawbacks. As shown in Figure 45. [MIURA YUKIYA 2006]

Figure 45 Example of X-Y Zoning method and OR maps

Figure 46 Operation Region Model

Currently the OR region method are focused on MOS fault diagnosis, however this research could be further investigated to see if the techniques can be applied to other components.

Designing the system for testability must be address simultaneously with the process of designing its functionality. This implies some modification to the circuit in order to enhance the process of test patterns generation which can be categorised into three main groups [DRAGFFY, GABE 2005]

• Ad- Hoc methods
• Structured design technologies
• Built In Test methods

Ad-hoc have methods evolved through the necessity to solve a particular testing problem rather than trying to solve the problem of testing complex circuits by using some design methodology listed below. The ad-hoc methods for improving the testability of a circuit have the advantage of not imposing severe constraints on the designer but have the disadvantage that they cannot be automated.

1. Insertion of testing points allowing internal node more accessible
2. Pin amplification – Pins available on board may be limited, however they can be multiplexed to act under certain conditions as test inputs/outputs.
3. Circuit partitioning – Additional gates are incorporated into the design to inhibit data flow along certain paths, effectively partitioning the circuit into smaller modules.
4. Control and observation switching – Signal lines whose logic values are easily controlled or observed are identified with multiplexers / de-multiplexers to improve access to nods where logic values are difficult to either control or observe. Test control signals can determine whether the lines are to be used for transmitting normal data or test data.
5. Test state registers – These are serial input, parallel output shift registers to increase the number of test control signals which can be applied to the circuit at any moment in time.

Matlab was used in this report to create bode plots from the transfer functions. However this is significant scope for this package to produce reliable understanding of how a circuit will function before build.

All of the objectives have been achieved.

1. Development of transfer function using Laplace Transforms

2 Development of simultaneous equations using Cramer’s rule

3. Measured circuit using computer simulation

4 .Determines circuit response using mathematical

5. Measured practical circuit

6. Build and test of demonstration board

7. Using Matlab for development of mathematics, bode plots and pole/zero plots

8. Faultfinding using the FaultFinder PCI Controller and using Testvue software

9. Further work investigated into design for testability

10. Further work investigated into Operational Region Models and X-Y Zoning methods

11. Further work investigated into IC Analysis

1. Gained an understanding in IV Measuring techniques

2. Gained an understanding in Lissajous figures

3. Improved awareness on developing mathematical transfer function to representing a circuit’s function

4. Gained an understanding in Automatic Optical Inspection and X-Ray Inspection

5. Gained a better understanding of Cramer’s rule

6. Better understanding of using Multisim 9

7. Design and build of circuits

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Figure 47 FaultFinder PCI Controller [DIAGNOSYS 2005]

Figure 48 Testvue Library [DIAGNOSYS 2005]

Abbreviations

BJT    =     Bipolar Junction Transistor

FET    =     Field Effect Transistor

ESD    =     Electro Static Discharge

IC    =     Integrated Circuit

LT     =     Laplace Transform

GPIB     =     General Purpose Interface Bus

CUT         =     Circuit Under Test

AXI        =     Automatics X-ray Inspection

ICT        =     In-Circuit testing

ATE         =     Automatic Test Equipment

TDM    =     Time Division Multiplexed

UUT        =     Unit Under test.

CCA        =     Circuit Card Assembly

CAD        =     Computer Aided Design

BOM        =     Bill Of Materials

QFP        =     Quad Flat Package

THT        =     Through-hole technology

CGA        =     Column Grid Array

OVHM         =     Oblique Views At Highest Magnification

OC        =     Open Circuit

SC        =     Short Circuit

SPICE        =     Simulation Program with Integrated Circuit Emphasis

OR        =     Operation Region

MOS        =     Metal Oxide Semiconductor

C        =     Cutoff region

L        =     Linear region

S        =     Saturation region

PCB        =     Printed Circuit Board